1. Field of the Invention
The present invention relates to a semiconductor device such as a semiconductor integrated circuit device or the like, and more particularly to a semiconductor device comprising a plurality of stacked semiconductor chips.
2. Description of the Related Art
Semiconductor integrated circuit devices have an integration density increased as the size of transistors that make up semiconductor integrated circuit devices decreases. Circuits for achieving many functions are installed on semiconductor integrated circuit devices each comprising a single semiconductor chip. Semiconductor memory devices, regardless of the types of memory circuits such as DRAMs (Dynamic Random Access Memories), SRAMs (Static Random Access Memories), or the like, also have a storage capacity increased as the size of transistors that make up semiconductor memory devices decreases.
In recent years, however, there have been growing demands in the art for more functionality and storage capability for semiconductor devices such as semiconductor integrated circuit devices and semiconductor memory devices than possible with the reduction of the size of transistors. It is understood that there are certain limitations on the efforts to reduce the size of transistors used in semiconductor devices. In view of the demands and the limitations, the development of new technologies has been sought for increasing the integration density of semiconductor devices. One of the technologies that have attracted attention in the art is a stacked semiconductor device, also referred to as a three-dimensional semiconductor device, comprising a plurality of stacked semiconductor chips. The stacked semiconductor chips provide a large-scale integrated circuit without the need for an increased apparent two-dimensional chip area or floor size.
Japanese laid-open patent publication No. H04-196263 (JP, 4-196263A) discloses a semiconductor device having a memory circuit integrated in a chip stacked on a semiconductor integrated circuit device. Japanese laid-open patent publication No. 2002-26283 (JP, P2002-26283A) discloses a multilayer memory device structure comprising a plurality of memory cell arrays disposed as multiple layers for an increased storage capacity.
If a plurality of semiconductor chips are multi-layered into a semiconductor device, then wiring between the stacked semiconductor chips is required in addition to wiring within each of the semiconductor chips. In conventional semiconductor devices having a plurality of semiconductor chips two-dimensionally arranged, wire bonding is often used for interconnections between the semiconductor chips. However, if wire bonding is applied to stacked semiconductor devices, then since wire bonding is a technology for interconnecting pads on the surface of a semiconductor chip, the following problems tend to occur:
(1) Because a pad provided on the surface of a chip needs a certain pad area such as 100 μm squared, the number of bonding wires that can be used on the chip is limited;
(2) Since pads disposed on the surfaces of stacked semiconductor chips are required to be positioned on outer edges of the stacked semiconductor chips so that they can be connected from outside of the chips, pads for bonding wires are not accessible if the stacked semiconductor chips are identical in shape to each other.
One solution to the above problems is through-connection that is provided through a plurality of semiconductor chips. Takahashi, et al. (K. Takahashi et al., Japanese Journal of Applied Physics, 40, 3032-3037 (2001)), proposed a silicon semiconductor chip having transistors formed thereon is thinned to a thickness of 50 μm, through-vias each having a size of 10 μm squared are formed in the silicon semiconductor chip, and plugs of metal are placed in the through-vias to provide through-connection for inter-chip interconnections. The through-connection allows inter-chip interconnections to be positioned two-dimensionally in the planes of chips, and makes it possible to provide several hundred inter-chip interconnections. In addition, since inter-chip interconnections extend through chips, a plurality of semiconductor chips that are identically shaped and sized can be stacked as a plurality of layers.
If a plurality of semiconductor chips are stacked according to the above technology, then it is possible to stack not only memory circuits, but also logic circuits and analog circuits, so that semiconductor memory devices can have an increased storage capacity and semiconductor integrated circuits can have many functions.
FIG. 1 shows an example of a conventional stacked semiconductor device which employs through-connection. In FIG. 1, three semiconductor chips 1801, 1803, 1806 are stacked. Second semiconductor chip 1803 and third semiconductor chip 1806 are stacked, successively in the order named, on first semiconductor chip 1801. First functional circuit 1802 disposed on first semiconductor chip 1801, second functional circuit 1805 disposed on second semiconductor chip 1803, and third functional circuit 1808 disposed on third semiconductor chip 1806 are electrically connected by through-connection 1804 extending through second semiconductor chip 1803 and through-connection 1807 extending through third semiconductor chip 1806.
For forming a through-connection through a semiconductor chip, it is necessary to form holes having a high aspect ratio such as 5:1, in the semiconductor substrate such as a silicon substrate, apply an insulating layer to inner side walls of the holes, and fill the holes with an interconnection material such as metal or polysilicon. Because of these steps, it is generally difficult to increase the accuracy with which to form through-connections, and hence the yield of through-connections has been low. If three or more semiconductor chips are stacked, then since through-connections need to be positioned accurately between the stacked semiconductor chips, the yield of products made up of stacked semiconductor chips is also low. In addition, when the number of stacked semiconductor chips is increased, e.g., three or four semiconductor chips are stacked, if even one of the stacked semiconductor chips suffers a through-connection failure, then the entire stacked semiconductor device becomes defective. Since the effect that a through-connection failure on one semiconductor chip has on a defect of a stacked semiconductor device increases depending on the number of stacked semiconductor chips, the fraction defective of stacked semiconductor devices increases as the number of stacked semiconductor chips increases.